Assignment 1
Q1
Simultaneously designing software and hardware concurrently.
Q2
a. A CPU b. A complete computer with a processor, memory, I/O c. A microcontroller with a fully functional system d. A SoC that is reprogrammable
Q3
#include <stdio.h>
int main() {
volatile uint8_t *memory_map = 0x5000;
uint8_t current_value = *memory_map;
printf("Current value of device register: %X\n", current_value);
*memory_map = 0x0017;
return 0;
}Q4
The give types of I/O synchronization are:
- Blind cycle
- Software waits and takes action irregardless if a device is ready or not
- Occasional polling
- A device is checked for readiness based on the convenience of the designers workflow (based on good times to check for readiness)
- Periodic polling
- The CPU waits a predetermined mount of time then checks if a device is ready
- Tight polling loop
- All processes are halted as the system enters an infinite while loop that waits for a condition to be true (device to be ready)
- Interrupt handling
- When a device is ready, it publishes an interrupt which tells the CPU to take action
Q5
From the perspective of a single device, tight polling is the lowest latency synchronization mechanism because software continuously checks for a device to be ready stopping all other processes. The CPI immediately takes action once the device is ready.
Q6
Interrupt handling as a synchronization method should be used for real-time / critical cases where the CPU needs to immediately service a device in question.
Interrupt handling could also be used if the CPU should be performing other tasks while waiting for a device to be ready.
In event-driven designs, interrupt handling is useful if the CPU needs to respond to an event published by a particular device.
Assignment 2
Assuming that data is generated spontaneously, as in, data is being generated during the transfer of data from the device to the CPU
There is also a consumer sensitive approach where data generation happens contiguously where you imagine the transfer needs to complete before the next byte can be generated
Q1
- (10ms * 1000)+max(2ms, 4ms) = 10004ms
- 1/2(10ms*1000)+max(4ms, 2ms)*2 = 5008ms
- (20ms)*1000)+max(2ms, 4ms)+3ms = 2007ms
- 1/2(20ms*1000)+max(2ms, 4ms)*2+3ms=10011ms
Basically here, device and cpu transfer times are bottle necks and are not cumulative. The device production times is cumulative based on how many bytes are produces, the synchronization mechanism adds a fixed time delay to the total clock time
The algorithm here is
Total time = time to produce 1000 bytes of data + transfer time for the final transfer + latency for synchronization
Q2
The job of the MAR is to hold the location of the address of the next instruction that the system bus needs to access to complete a transaction. Since the CPU acts only as the controller of a system bus transaction, the CPU only ever needs to write to the MAR and therefore writing is unidirectional from the CPU.
The MDR holds associated data for a system bus transaction that is at the address that the MAR is holding. Since data could go from the CPU to the system bus or the other way around, the MDR must be bi-directional.
Example
CPU reading data from memory
- The CPU initiates read
- The CPU writes an address to the MAR
- The MAR writes address to the system bus
- The system bus reads data from memory
- the system bus writes that data from memory to MDR
- CPU reads data from the MDR
Basically, flip this in reverse for a write operation
Q3
Reading synchronously:
- Consistent transaction time but you need to wait for the slowest transaction for every transaction Reading asynchronously:
- Allows you to do other things while waiting for a device to be ready but may be slower since you aren’t constantly checking state + more control signals need to manage the transaction
Assignment 3
Q1
See my notebook for solutions.
Q2
When there are multiple drivers sharing a bus
Q3
No if they are used correctly, their whole point is to eliminate conflicts
Q4
Not if they are used correctly since these can only output a 0 or Z and the Z will be overwritten if a “conflict” occurs
BASICALLY OD AND OS CANNOT CAUSE CONFLICTS
Q5
Because they use passive resistances to pull-up which increases the rise/fall time of a signal
Q6
See my notebook for solutions.
Assignment 4
Q1
a) Skew time is the maximum difference between propagation time (fastest bit to slowest bit) b) Propagation time is the time it takes a signal to reach the device it is interacting with c) Setup time is the minimum amount of time before the next rising clock edge that a signal should be stable for to make sure it can be read properly d) The amount of time data is held stable for to be read from after the rising clock edge
Q2
See my notebook for solutions.
Q3
Synchronous Bus Transfers
- Common view of time (common clock)
- Each transfer finishes in a single period
- No guarantee that a transfer will finish in this clock cycle
- As fast as the slowest device Asynchronous Bus Transfers
- Uses two handshake signals to communicate timing
- Time required to complete a transfer could vary (which is an advantage)
- Allows you to do other things while you wait
- Generally slower than synchronous transfers unless there is a large timing variety between device timing
Q4
See my notebook for solutions.
Assignment 5
Q1
a. A control register used to control bidirectional data lines where the value in this register is used to control the enable bit of a tri-state that controls whether the DI or DO register is used
b. Persistent data is data that holds for a long time or data that needs to be removed by the controller or peripheral
c. Transient data is data that holds for t_hold and then is removed (temporary data)
Q2
See my notebook
Q3
In band:
- Using in-band techniques allow you to send control signals in the same way that data is sent, but you need a mechanism to distinguish the two types of information being sent, this could be easier to send information since you only need one mechanism but its harder to distinguish the data
- Out-of-band techniques require two different mechanisms to send data but by using such a technique, they can’t be mixed up, but it requires another method of decoding
In-band techniques involve more complex hardware/software to distinguish what control information is whereas out-of-band techniques could involve an additional wire or hardware that handles extra signalling, the timing of signals also needs to be considered here
Q4
Using passive pull-up:
- Slowing rising edge time but fast falling edge time
- One pull up resistor per line
- Can’t drive active 1 or 0, no high impedance state Using tri-states
- Fast rising and falling edge
- More complex hardware
- Impedance state
- Can drive actively Software complexity is the same for both
Q5
See my notebook
Q6
See my notebook
Q7
A-b) See my notebook
c)
uint8_t START = 0x04
uint8_t DATA_READY = 0x02
#define DATA_MASK (uint8_t)0x0F
int read() {
uint8_t data = 0;
uint8_t * data_in = DATA_IN_ADDR;
unit8_t * data_out = DATA_OUT_ADDR;
// Start sensor
*data_out = START;
// Assume that data_ready is cleared
// Poll sensor for data
// get data by masking (this basically clears everything except the last 4 bits)
data = (int)(*data_in & DATA_MASK);
*data_out = ~START;
return data;
}Assignment 6 Part 1
Q1
- Infinite bandwidth
- =
- Open loop gain is infinite
- Zero output impedance
- Infinite input impedance
Q2
a) , ,
b) Max current occurs when all switches are closed which has a higher current than the op-amp rated current, therefore the values are not suitable.
Q3
Cheaper and more accurate
Q4
You should choose the 10-bit DAC because even thought the step size is not as fine as the 12 bit, since both DACs have the same error, the error is larger than the step size for the 12 bit DAC.
I calculate DNL in my notebook and formally answer there. Since DNL of the 12-bit DAC is > 1, it suffers from monotonicity error.
Q5
See my notebook