Serial Interfacing

Why Serial?

Bottom line, its cheaper.

We use less pins, less wire, therefore, less cost

Channels

• Simplex: Unidirectional data flow (transmitters and receivers)
• Half Duplex: Bi-directional, one-way at a time
• Full-Duplex: Simultaneous bi-directional

Synchronization

We need synchronization to interpret serial signals:

• Bit Synchronization: How big is each bit and where does it start and stop?
  • Bit Rate Synchronization: The time that elapses between the start of one bit and the start of the next
  • Phase Synchronization: Given a known rate, how is the middle, or start of any bit found?
• Byte Synchronization: Where do bytes start and stop?
• Block Synchronization: Where do blocks start and stop?

Bit Synchronization

The easiest way to do this synchronization is to have a clock where one edge of the clock is used to sample the data line for example.

We also need some marker to notate where bytes start,

Data Representations as Electrical Signals

On/Off

• 1 is high and 0 is low, pretty easy and what we’re used to Bipolar
• Same as On/Off but centred around 0 RZ (Return to Zero)
• Goes high with 1 and returns to 0 before the bit is done (transition is halfway through the bit) Machester (Split Phase)
• Changes in the middle of the bit but no edge when you switch bits (staying the same bitwise causes an edge both in the transition area and in the middle of the bit but going from 0 to 1 causes no edge)
• Splits in the middle, and returns to 0 if the bit doesn’t change Differential Encoding
• Edge means 0 and no edge means 1, data can be interpreted even if its inverted basically just change the signal on a 0 bit NRZI (Inverted or Interval
• Edge means 1 and no edge means 0 so transitions represent bits

One Byte Serial Interface

Shift registers are used to convert between serial and parallel data streams

SRout

When can you write to SRout? You can write to SRout when SRout is empty, and then XMIT has new data.

Transmitting Steps

• Data is loaded into XMIT register in parallel from the system bus
• When $S{R}_{out}$ is idle, data is transferred from XMIT to $S{R}_{out}$
• Data is shifted out serially by the Tx clock

Recieve Steps

• Data is shifted into the $S{R}_{in}$ register by the Rx clock
• When $S{R}_{in}$ is full, data is transferred into the RCV register
• Data is transferred into the system bus

Synchronous vs Asynchronous

Synchronous: Shared clock
Asynchronous: No shared clock

Significant Errors:

• Corrupted data received due to noise on the channel
• Erroneous data caused by timing problems

Clocks and Timing

The transmit and receive clocks do not need to be at the same data rate, the clock is an external interface. Sometimes, a local oscillator can be used for the transmit and receive clocks.

If you sample a bit on a rising vs falling edge, you get different data. Ideally, we want to sample a bit in the middle of the bit.

There are two registers run in each direction for buffer time using a shift and RC register so that we have an entire byte time to read before data is copied.

Before communication begins, the two ends need to agree on:

• Timing
• Control
• Format
• Data representation
• Electrical Signalling

Asynchronous Protocols

Assuming both channels know the baud rate, we need to convey the phase of the Tx clock to the receiver.

The falling edge of the Tx clock resets the counter to 0, since we know the baud rate, we know how long we need to wait to find the middle of a bit for sampling.

Potential Issues:

• Data can’t be clocked into the receiver using the same transmission clock
• Only a nominal transmission frequency spec exists
• No direct phase synchronization We need a way to extract the phase of the clock such that we can sample the middle of a bit since we should know the nominal frequency

An Asynchronous Frame:

• Bit 1 is the start bit which is a “0: and indicates a data byte is going to start
• We then have our data bit where Bit 7 could be a parity bit
• Bit 8 and 9 are stop bits which are “1” to indicate the end of data, this ensures the start bit has a falling edge

Bit Sampling Steps

1. Wait for falling edge (start bit)
2. Wait for 0.5 bit times
3. Verify serial data is still 0
4. Wait 16 clock times and sample first bit
5. Wait 16 clock times and sample ith bit
6. Wait 16 clock times and sample last bit
7. Wait 16 clock times (1 bit time)
8. If data = 0, there is a framing error
9. If there are to be 2 stop bits repeat steps 7-8 once more
10. Indicate byte has been received and go to step 1

Clock Errors

If the clock rate drifts more than 0.5 bits, the information detected will be corrupted but we have so much inherent error checking we will catch this. Therefore, the frequencies of the derived clocks can’t differ by more than 5%.

$\Delta T=\left|\frac{1}{f_{Rx}}-\frac{1}{f_{Tx}}\right|$
if $B\Delta T>\frac{1}{2}\frac{1}{f_{Tx}}$ then the shift at the end of $B$ bits is larger than 0.5 bits.

Overhead: This is $\frac{\text{Number of non data bits in a frame}}{Totalnumberbitsinaframe}$

Some Errors

• Framing Error: An incorrect frame has been detected where a stop bit is incorrect
• Overrun Error: The data at the transmitter and receiver is transferred at a time convenient to the controlling processor. Therefore, serial data could arrive too quickly, or the transmitter could send data faster than the serial data allows
• Parity Error: The parity of received data and the parity bit don’t match
• Start Bit Error: Reading a false start bit

Parity Bits

The parity bit is set to 1 or 0 depending of if our communication is even or odd parity. Even parity is an even amount of 1s and odd parity is an odd amount of 1s. Parity error is when this doesn’t like up with our parity setting.

Mismatching stop bits
If $S{B}_{Tx}>S{B}_{Rx}$ we have extra idle time but its all good
If $S{B}_{Tx}<S{B}_{Rx}$ there is a problem since we get a framing error (the receiver looks for a stop bit where it gets a start bit)

Bit Byte Block

Synchronization	Technique	Comments
Bit Sync	By agreement	Can be done in software
Bit Sync Phase	Start/stop bits	Detect failing edge to find start bit
Byte Sync	Start/stop bits	Once bit 0 is detected, we know we have a new byte
Block Sync	N/A	To be discussed…

Downsides:

• Low data rates
• Not robust
• Hw required that can’t easily be replaced

Synchronous Protocols

Reminder

Reminder that synchronous means shared clock here

Advantages:

• Reduces overhead
• Eliminates clock skew problem
• Increases data transmission

Clock Embedding

You can actually embed your clock info in your data using something like Manchester encoding.

On the transmit side, we merge the clock and data and on the receive side, we decode that signal

Synchronous Bit Sync

Using Manchester encoding to embed the clock signal…

• The extraction circuit wants to find the edge in the middle of the Manchester encoded bit

Synchronization methods

• I2C: Use special signalling for stop and start combined, the clock only pulses when information is sent
• SPI: Use a dedicated clock line, prior agreement on data transfer

I2C

Designed for short-distance communication between multiple chips in a single device.

• Up to 1008 devices → bit addressed
• Controller 2 to Peripheral 2 communicates with a serial data and serial clock line
• Sends data from MSB to LSB

I2C has an acknowledge bit from the controllers perspective on the SDA (Serial Data Line)
More Details

• The clock idles low while the data line idles high
• The ACK bit is 0 for an acknowledge but if its 1 that means the addressed peripheral did not respond
• On a read the ACK bit is sent by the controller, on a write it is sent by the peripheral
• Start condition: SDA goes low before the SCL
• Stop condition: SDA goes high after SCL Advantages
• Dedicated clock line removes need for known clocks are the device level
• No start/stop bit overhead
• Communication is not limited to 2 devices
• Uses open-drain drivers so that multiple controllers and peripherals can share the line Disadvantages
• ACK overhead
• limited to slower speeds

Synchronization

Bit: The clock line syncs pulses
Byte: One clock pulse is sent at the start of a byte, the rest of the time the clock idles high
Block: The SDA goes low before the SCL to indicate the start of a block and goes high after the SCL to indicate the end of a block

SPI

The Serial Peripheral Interface is used to communicate between the single controller and peripherals on the same device

Runs on chip select (active low) which starts the clock.

The data lines here include:

• COPI (Controller out peripheral in)
• CIPO (Controller in peripheral out) SPI uses a serial clock.

Speed

Runs from 20-66 MhZ

Weird Data Stuff

For the COPI line, you could directly connect to all the peripherals from the controller or you could daisy chain this line with one CS line that turns on all the bits, and propagates data from the closest peripheral to the farthest peripheral.

This work on the output and input side

Advantages

• Higher speeds
• Implemented with simple hardware (shift registers) Disadvantages
• Requires multiple CS lines or additional shifting of data bits
• Requires more pins
• communication format has to be well defined

USB

The goals of USB

The goal here was to replace all those cables and connectors that you needed with SPI and I2C with a single cable.
It’s plug and play, and its expandable and low cost.

USB 3.0 is much faster now due to the use of a full duplex.

USB C works by basically reflecting the interface from one side to the other so that way if its flipped, the pin types don’t change.

Signalling

• Pull up resistors are used to differentiate high and low speed devices
• Pull down resistors to make sure the lines aren’t floating
• D+ and D- are half duplex which is unidirectional (these are the differential drivers)
• Different drivers and receivers here
• Max cable skew between D+ and D- is 100ps

USB receivers

USB uses differential receivers which detect the difference between 2 wires (in this case $D_{+}$ and $D_{-}$) to help signal integrity

USB also uses single ended receivers which detect voltage relative to ground which is used for control signals (in this case, whether we are doing high or low speed transfers)

Data Transfer

• Only the root hub can initiate transfers
• Each transaction is usually made up of 3 packets
  • The USB Token Packet: Selects the peripheral
  • The USB Data Packet: Payload information
  • The USB Handshake Packet: Ensures data has been received (for synchronization)

USB PID

USB PID has 16 PID values which are encoded using 8 bits for error detection (one nibble is the ID and the other is it’s inverse)

• USB SOF Token Packet: In USB a frame is used to provide some synchronization to facilitate data transfer
• An SOF packet is sent out once per millisecond to indicate the start of a new cycle
• USB IN/OUT Token Packets: Used for interrupt, bulk, control, and isosynchronous packets. These packets provide the in and out transfer I/O endpoints
• USB ACK: Receipt of a data packet
• USB NACK: Unable to accept or return data, also used during pilling to indicate no new data is available
• USB STALL: Target is unable to complete transfer and software is required
• USB Interrupt Transfer: Each device must be polled at a regular interval, during polling the device could loose data but each piece of data must be delivered
• USB Bulk Transfer: Used by block transfer devices. No particular time constraint here. Each piece of data needs to be delivered.
• USB Isochronous Transfer: For real time data transfer. Each piece of data doesn’t need to be written but the transfer rate needs to be constant.
• USB Control Transfer: Used to set up devices

Synchronization

• Data rate is specified by the pull up resistors
• USB uses differential signal encoding but refers to it as (NZRI)
• Zeros cause transitions and ones do not cause transitions
• Bit stuffing maintains clock edges to keep the clock synchronized it is used to make sure that data isn’t accidentally interpreted as a control signal. In terms of keeping the clock synchronized, bit stuffing basically forces a transition to make sure everything is all good.
• We need six 1’s and then one 0 to trigger and edge otherwise you loose data
• The 1 ends a byte so that we know where the byte boundaries are

Drawing Graphs

USB has 2 signals $D_{+}$ and $D_{-}$ which are inverses of each other, basically for graphs draw $D_{+}$ and then flip it for the complimentary signal. This is for all USB but I think USB C takes advantage of this for the interface?

Serial Trade-Offs

	Benefit	Drawback
UART	Bi-directional No blocks = Simple Simple	Slow Limited to 2 devices
$I^{2}C$	Only 2 lines required (SDA, SCL) Uses acks to ensure responsiveness	Half duplex = slow = one direction at a time Format of bytes per transfer must be pre-agreed upon
SPI	Fast Simple HW (1 shift register)	1 CS line or daisy chaining which requires more shits to get to the end of the chain Data format must be agreed upon beforehand
USB	Fast Full-duplex Plug + play	Super complicated and transactions are complex