Synchronous Bus Write

Similar to a Synchronous Bus Read

Timing

After sending the address and data, everything happens from the peripherals view of time

Flow

1. Send address and data from controller to peripheral
2. Wait for propagation and skew time
3. Wait for margin time (falling edge)
4. Wait for the select, store (after device is selected, get everything ready to be stored but don’t actually store) and margin time (margin time aligns actual storage right at the end of the transaction on the next rising edge)
5. Before the next rising edge, wait for setup time (actually stores the data)
6. On rising edge, start hold time (where hold time is 0 ideally)
7. The controller removes the address and data from the peripheral (on next rising edge but occurs after setup and hold time)

The normal clock and register clock are inverted from each other…
Why?

• To minimize skew time?
• On the falling edge of the normal clock, the register clock goes high because data is ready and the register can do things?

Clock expressions
Normal Clock
$!Clock\cdot AddressDecoded\cdot \frac{!R}{W}$
Register Clock (this gets you a write lined up with a rising clock edge) $!\left(!Clock\cdot AddressDecoded\cdot \frac{!R}{W}\right)$